The present invention relates to a method and apparatus for managing a received and modulated signal in general and to a method and apparatus for managing a time synchronization mechanism in particular.
Reference is now made to FIGS. 1A and 2. FIG. 1A is a prior art graphic illustration of the amplitude measurement versus time T, of a signal, generally referenced 1.
FIG. 2 is a schematic illustration of a prior art apparatus, generally referenced 20, for acquiring the accurate synchronization for a received signal.
Apparatus 20 includes a voltage controlled clock (VCC) 22, an early detector 26, for detecting the beginning section of a received signal, a late detector 24, for detecting the end section of a received signal, a metric processor 40, connected to the output of the early detector 26, a metric processor 42, connected to the output of the late detector 24, a subtracting unit 30, connected to the metric processors 40 and 42, a filtering unit 32, connected to the subtracting unit 30 and to the VCC 22 and a signal detection unit 28, connected to the VCC 22.
The early detector 26 is connected to VCC 22 via a time phase advance unit 44, which advances the clock signal provided by VCC 22, by a predetermined time period xcex4. The late detector 24 is connected to VCC 22 via a time phase delay unit 46 which delays the clock signal provided by VCC 22 by predetermined time period xcex4.
The apparatus 20 further includes an equalizing unit 34 connected to the signal detection unit 28. The equalizing unit 34 is required for processing channel signals which include inter-symbol interference, such as multipath fading channels.
In the present example, the early detector 26 of the present example includes a matched filter 54 and a sampler 36 connected therebetween, the late detector 24 includes a matched filter 56 and a sampler 38 connected therebetween and the signal detection unit 28 includes a matched filter 50 and a sampler 52 connected there between.
The object of apparatus 20 is to perform detection of a received signal.
Referring back to FIG. 1A, the accurate synchronization for the signal 1 is represented by the phase time period 2. The accurate location of phase time period 2 is unknown and therefore, has to be detected and determined. In the prior art, this is done by providing signal detectors which detect the signal in at least two time periods:
i. an early detector, such as early detector 26, which detects the received signal over a first time period 4 viewing the beginning section of the signal 1; and
ii. a late detector, such as late detector 24, which detects the received signal over a second time period 6, viewing the ending section of the signal 1.
Each of the detectors 24 and 26 produces an output with a magnitude that is proportional to the portion of the signal 1 detected thereby. Detectors 24 and 26 provide their output to the metric processors 42 and 40, respectively. Metric processors 40 and 42 compute either an absolute value of this output or its square value.
When one detector detects a larger portion of the signal than the other detector, the output provided by the corresponding metric processor, connected thereto, will be higher respectively. Accordingly, the sampling phase should be shifted towards the detector which detects the least amount of signal, so as to achieve equilibrium therebetween.
In the present example, when late detector 24 detects a portion of the received signal which is larger then the one detected by the early detector 26, this indicates that the phase time period 2 is shifted to the right with respect to the original signal 1. Accordingly, the original signal 1 has to be shifted to the left.
If, on the other hand, the late detector 24 detects a smaller portion of the signal 1 than the one detected by the early detector 26, then the phase time period 2 is shifted to the left with respect to the original signal 1. Accordingly, the original signal 1 has to be shifted to the right.
In apparatus 20, early detector 26 performs a convolution of the input signal with the matched filter 54 over the beginning section of the received signal while late detector 24 performs the convolution with the matched filter 56 over the end section of the received signal. The results of these two convolutions are fed to the metric processors 40 and 42 respectively, which in turn, provide their output to subtracting unit 30. The subtracting unit 30 subtracts the output provided by metric processor 40 from the output provided by metric processor 42.
The result of the subtraction determines if the VCC 22 should operate under a new sampling phase thereby determining a new location of the phase time period 2 with respect to the original signal.
The subtracting unit 30 provides the result of the subtraction to the filtering unit 32 which modifies, accordingly, a suitable signal and provides it to the VCC 22, as feed-back. The VCC 22 adjusts the phase respectively. This operation is called a delay lock loop (DLL).
Thus, the signal detection unit 28 should be provided with a well-synchronized signal for decoding. This DLL apparatus is a simplified and efficient realization of the optimal maximum likelihood (ML) time synchronizer. Another implementation for an ML time synchronizer, known in the art, is to sample the received signal at a plurality of synchronization phases and to determine the optimal phase therefrom.
Such implementations perform very well on channels with no, or very little inter-symbol interference (ISI). For channels with high ISI, such as multipath fading channels, the performance of the prior art apparatus described hereinabove degrade considerably since ISI causes the symbol pulse shape to be smeared over a longer period of time. As a result, the output of the early and late detectors is now effected by a large number of symbols. In a multipath fading channel, the shape of the symbol pulse received at the receiver changes arbitrarily in time, according to the gains of the fading paths, so the optimal sampling phase is no longer well defined.
In channels with high ISI, detectors such as signal detecting unit 28 have a very high symbol error rate. This requires the use of an equalizer, such as equalizer 34, in order to lower the apparatus overall symbol error rate.
In many types of channels, such as multipath fading channels, uses of a non linear equalizer, such as a maximum likelihood sequence estimation (MLSE) equalizer or a decision feedback equalizer (DFE), results in improved performances. It should be noted that the MLSE equalizer is the optimum equalizer in terms of sequence error rate.
When using an equalizer, especially a non-linear one, the sampling phase that will result in the best equalizer performance is a complex function of the input signal. The simple metrics utilized by metric processors 40 and 42 are far from being optimal.
According to some prior art methods, the detection process is performed using additional detecting units for acquisition of other areas of the received signal, such as time periods 8 and 10 (FIG. 1A).
In a multi-path channel, a received signal includes a plurality of echoes which often overlap. It will be appreciated that it is considerably difficult to detect a conventional signal in a multi-path situation.
Reference is now made to FIG. 1B which includes three graphic illustrations, generally referenced 61A, 61B and 61C, of the amplitude measurement versus time T of a signal, generally referenced 63.
Signal 63 includes transmitted symbols 60, 62 and 64 traveling through a channel 66. Channel 66 represents the various paths, often caused by reflections from various objects, through which each transmitted symbol may travel. These reflections determine the channel impulse response 68 of channel 66. Thus, channel 66 influences each of the symbols 60, 62 and 64, according to channel impulse response 68, so as to produce received symbols 70, 72 and 74 respectively. Each received symbol is the result of a convolution between the respective transmitted symbol and the channel impulse response.
The received signal 76 is a summation of received symbols 70, 72 and 74. The received signal 76 is received by a receiver and is provided to apparatus 20 for processing. It will be noted that the received symbol 76 may also include noise.
Channel taps correspond to the effect of neighboring received symbols on the current received sample. For example, the value of a sample si sampled at the output of the receive filter, is given by
Si=xcexa3n=xe2x88x92L1L2hnaixe2x88x92n
wherein the ai are the transmitted symbols (xe2x88x92∞ less than i less than ∞); and
hn are the gains of the channel taps (xe2x88x92L1xe2x89xa6nxe2x89xa6L2). L1 and L2 define the length of channel memory which, in turn, defines the number of neighboring symbols which affect each sample.
U.S. Pat. No. 5,533,066 describes a method which attempts to provide an accurate estimation of a maximum likelihood sequence using detection of the signal at a plurality M of points using a metric which relates to the bits of data provided by the signal detection unit 28.
It is an object of the present invention to provide a novel method and apparatus for acquiring and tracking the sampling phase of a signal with inter-symbol interference.
In accordance with the present invention, there is thus provided apparatus for providing an optimized sampling phase to a received signal in a given channel, the received signal including inter-symbol interference. The apparatus includes a voltage controlled clock (VCC) for providing a VCC sampling phase, a first signal detector, connected to the VCC, for sampling the signal according to an advanced sampling phase which is advanced by a predetermined value xcex4 with respect to the VCC sampling phase, thereby producing a first sampled signal, a second signal detector, connected to the VCC, for sampling the signal according to a delayed sampling phase which is delayed by a predetermined value xcex4 with respect to the VCC sampling phase, thereby producing a second sampled signal, a first channel metric estimating unit, connected to the first signal detector, for obtaining a first estimated metric value from the first sampled signal, a second channel metric estimating unit, connected to the second signal detector, for obtaining a second estimated metric value from the second sampled signal and a subtracting unit, connected to the first channel estimating unit and to the second channel estimating unit, for subtracting the second first estimated metric value from the second estimated metric value, thereby obtaining a phase correction signal according to which, the VCC sampling phase is to be corrected.
The first and second estimated metric values are selected from the group consisting of: a symbol-error-rate, a bit-error-rate, a cutoff-rate, a channel capacity and the like.
The apparatus may further include a filtering unit, connected between the subtracting unit and the VCC for filtering the phase correction signal and providing it to the VCC.
The apparatus according to the invention may further include a signal detecting unit connected to the VCC, for detecting the received signal, thereby obtaining a plurality of samples.
The apparatus may also further include an equalizing unit connected to the signal detecting unit, for detecting symbols contained in the samples thereby producing detected symbol decisions and a decoder, connected to the equalizing unit, for decoding the received coded signal according to the detected symbol decisions.
Each the detected symbols may include quality.
According to one aspect of the invention the estimated metric value defines a metric selected from the group consisting of:                     -                  K                      δ            min                              ⁢              Q        ⁡                  (                                                                      6                                                            M                      2                                        -                    1                                                  ·                                                      E                    s                                                        N                    o                                                              ⁢                              xe2x80x83                            ⁢                              δ                min                2                                              )                      ;          xe2x80x83        ⁢                  -        Q            ⁢              (                                            6                                                M                  2                                -                1                                      ·                                          E                s                                            N                o                                                    )              ;                                -                      1                          k                                      ⁢                  xe2x80x83                ⁢                  e                      -                          k              2                                          ;              xe2x80x83            ⁢              -                  e                      -                          k              2                                          ;              xe2x80x83            ⁢              -                  Q          ⁢                      (                                                            E                  s                                ·                                  γ                  ∞                                                      )                              ;        ⁢          xe2x80x83                  -                        log          2                ⁢                  (                      1            +                                          (                                  M                  -                  1                                )                            ⁢                              e                                  -                                                            E                      s                                                              N                      o                                                                                                    )                      ;          xe2x80x83        ⁢          and      ⁢              xe2x80x83            -                        e                      -                                          E                s                                            N                o                                                    .            
According to another aspect on the invention, there is thus provided a method for operating a system for acquiring and tracking the sampling phase of a received signal, the received signal being sampled according to a signal sampling phase, the received signal including a plurality of symbols, the system including an equalizer operating on the received sampled signal and a error correction decoder for decoding the processed signal, there is claimed a method for acquiring and tracking an optimized sampling phase the method includes the steps of:
a. detecting the received signal in at least two sampling phases, thereby obtaining a sampled signal for each the sampling phases;
b. for each the sampled signal, estimating a estimated metric error rate value at the equalizer output;
c. adjusting the signal sampling phase according to the estimated metric error rate values; and
d. adjusting the sampling phases according to the estimated metric error rate values.
Each sampled signal may include at least one sample. Each the sample may be a representation of an estimated symbol.
The estimated metric rate value defines a metric selected from the group consisting of:                     -                  K                      δ            min                              ⁢              Q        ⁡                  (                                                                      6                                                            M                      2                                        -                    1                                                  ·                                                      E                    s                                                        N                    o                                                              ⁢                              xe2x80x83                            ⁢                              δ                min                2                                              )                      ;          xe2x80x83        ⁢                  -        Q            ⁢              (                                            6                                                M                  2                                -                1                                      ·                                          E                s                                            N                o                                                    )              ;                                -                      1                          k                                      ⁢                  xe2x80x83                ⁢                  e                      -                          k              2                                          ;              xe2x80x83            ⁢              -                  e                      -                          k              2                                          ;              xe2x80x83            ⁢              -                  Q          ⁢                      (                                                            E                  s                                ·                                  γ                  ∞                                                      )                              ;        ⁢          xe2x80x83                  -                        log          2                ⁢                  (                      1            +                                          (                                  M                  -                  1                                )                            ⁢                              e                                  -                                                            E                      s                                                              N                      o                                                                                                    )                      ;          xe2x80x83        ⁢          and      ⁢              xe2x80x83            -                        e                      -                                          E                s                                            N                o                                                    .            